The present invention relates to solid-state imaging apparatus capable of preventing a degradation of sensitivity and a saturation based on the fining of pixel and to imaging system using the same.
A prior-art solid-state imaging apparatus using MOS transistor is constructed as shown in FIG. 1. Referring to FIG. 1, what is denoted by 100 is a pixel section which in this case is shown as constructed by arranging pixels 101 indicated by P11 to Pnm into n columns by m rows. 200 is a vertical scanning circuit for selecting pixels by the unit of row and causing pixel signal of the pixels of the selected row to be outputted to a vertical signal line 50 which is provided for each column. 400 is a horizontal read circuit by which the pixel signals corresponding to one row selected by the vertical scanning circuit 200 and outputted to the vertical signal line 50 are fetched through a fetch switch 40 controlled by fetch pulse φT so as to output signal of the pixels of that row from an output terminal 401 in time sequence in order of their arrangement in the horizontal direction. 60 is a current supply connected to the vertical signal line 50.
The construction of pixel 101 used in this solid-state imaging apparatus will now be described by way of FIG. 2. Referring to FIG. 2, PD is a photodiode (photoelectric conversion device), and FD is an electric charge retaining section consisting of a capacitor device for detecting signal electric charges generated and accumulated at the photodiode PD. Here, the electric charge retaining section is shielded from light. M1 is a transfer transistor for transferring a signal of the photodiode PD to the electric charge retaining section FD, which is controlled by transfer pulse φTR-i. M3 is an amplification transistor which forms a source follower amplifier with the current supply 60 provided on the vertical signal line 50. The signal of the electric charge retaining section FD is amplified by the amplification transistor M3 and is outputted to the vertical signal line 50 through a select transistor M4. The select transistor M4 is controlled by select pulse φSE-i. M2 is a reset transistor controlled by reset pulse φRS-i, for controlling connection between the input section of electric charge retaining section FD as well as of amplification transistor M3 and a pixel power supply VDD.
Here, select pulse φSE-i, transfer pulse φTR-i, and reset pulse φRS-i are outputted from the vertical scanning circuit 200 shown in FIG. 1 and are indicated by φSE-1 to φSE-m, φTR-1 to φTR-m, and φRS-1 to φRS-m in FIG. 1.
Before describing operation of the solid-state imaging apparatus shown in FIG. 1, operation of the pixel shown in FIG. 2 will be described below with reference to a timing chart shown in FIG. 3 and potential diagram of each section of photodiode PD, transfer transistor M1, and reset transistor M2 shown in FIGS. 4A to 4D. Referring to the timing chart of FIG. 3, it is supposed that, at point in time t1, signal electric charges generated by a light signal is accumulated as shown in FIG. 4A at photodiode PD of the pixels 101 on selected one horizontal line. When “H”-level reset pulse φRS-i for turning ON the reset transistor M2 is given at time t1, the electric charge retaining section FD is reset to the pixel power supply VDD as shown in FIG. 4B.
Next the reset transistor M2 is turned OFF, and “H”-level transfer pulse φTR-i for turning ON transfer transistor M1 of the pixels of the selected row is given at time t2. The signal electric charges accumulated at photodiode PD is thereby transferred to the electric charge retaining section FD as shown in FIG. 4C. After that, the electric charge retaining section FD is retained at a value based on light signal even when the transfer control pulse φTR-i is brought to “L” level to turn OFF the transfer transistor M1. On the other hand, all of the signal electric charges accumulated of the photodiode PD is transferred to the electric charge retaining section FD so that it attains an empty condition of signal electric charge as shown in FIG. 4D, i.e., reset condition of photodiode PD. The photodiode PD then starts accumulation of signal electric charges generated thereafter by light signal.
The select pulse φSE-i then is driven to “H” level at time t3 so that pixel signal obtained by amplifying signal of the charge retaining section FD is outputted to the vertical signal line 50. After that, pixel signals are outputted from the output terminal 401 through the fetch switch 40 and horizontal signal read circuit 400.
An operation of the solid-state imaging apparatus shown in FIG. 1 will now be described by way of a timing chart shown in FIG. 5. The reset pulse φRS-1 of the first row is outputted at time t1 from the vertical scanning circuit 200 to reset the electric charge retaining sections FD of the first row. Next at time t2, transfer pulse φTR-1 of the first row is outputted from the vertical scanning circuit 200 to transfer signal electric charges accumulated at the photodiode PD of the first row to the electric charge retaining section FD. Subsequently at time t3, select pulse φSE-1 of the first row is outputted from the vertical scanning circuit 200 to output pixel signals of the first row to the vertical signal line 50. At this time, fetch pulse φT is concurrently driven to “H” level so that the pixel signals outputted to the vertical signal line 50 are fetched to the horizontal read circuit 400 and are outputted from the output terminal 401 at and after time t4 in time sequence in order of their arrangement in the horizontal direction. In FIG. 5, this signal of the output terminal 401 is indicated by Sig.
The accumulation period of pixel signal of the first row outputted here is the period indicated by T1 in FIG. 5, i.e. from time t0 at which the transfer of signal electric charges is effected to reset photodiode PD in the previous frame to time t2 at which it is transferred in current frame. A similar operation as for the first row is also effected for the rows of the second and after so that the pixel signals of all pixels of the pixel section 100 are outputted from the output terminal 401.
Further of thus described solid-state imaging apparatus using MOS transistor, construction has been proposed to improve its characteristic by providing additional device within the pixel shown in FIG. 2. Japanese Patent Application Laid-Open 2003-87657 and Japanese Patent Application Laid-Open 2004-165467 for example disclose the providing of a storage device and/or CCD respectively for each pixel to avoid an image distortion which occurs when an image of moving object is taken due to the fact that the electric charge accumulation time, i.e. charge accumulation start timing and charge accumulation end timing are different from one line to another.